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A.1 Conventional Multi-Angle Evaporation

Since the 1970s, Josephson tunnel junctions have been formed by multi-angle (shadow) evaporation of superconducting electrodes separated by an in-situ-grown insulating barrier. Many groups now use a three-stage process that routinely yields coherence times in the hundreds of microseconds.

Josephson junction made using shadow evaporation. Figure adapted from [3]

Josephson junction made using shadow evaporation. Figure adapted from [3]

Stage 1: Photolithography of linear components. The substrate is first cleaned to minimize two-level systems (TLS). Common choices are sapphire (low loss but hard to process) and high-resistivity silicon (mature industry but larger surface and bulk losses). A Piranha clean removes organic residue; for Si, buffered oxide etchant (BOE) removes lossy surface SiO2. Transfer time to the deposition chamber is minimized to prevent oxide regrowth. The superconductor is then deposited: Al and Nb can be sputtered directly, whereas alpha-Ta requires either substrate heating to about 500 C or a thin Nb seed layer. Microwave components (resolution about 1 micron, suited to features greater than 10 microns) are patterned with a near-UV laser, offering fast write times (under about 100 min for a 300 mm wafer), then developed and etched.

Stage 2: Junction definition by e-beam lithography. Ambient oxides are removed before Al deposition, by BOE for Nb and Ta, or by in-situ ion milling for Al (which BOE etches), with care to avoid ion-induced roughness. A bilayer e-beam resist forms the bridges and overhangs needed for shadow evaporation. Two styles dominate: the Dolan style uses a suspended resist bridge, with junction size set by bridge geometry, evaporation angle, and resist height, making it sensitive to resist-height variation but essential for high-inductance circuits; the Manhattan style uses a cross-shaped trench that fixes junction size and is insensitive to resist-height variation, but complicates array fabrication. Junctions are finalized by double-angle Al evaporation with intervening in-situ oxidation, the self-limiting AlOx thickness setting the Josephson energy. Dynamic oxidation (constant pressure via modulated oxygen flow) improves uniformity over static oxidation; residual radial nonuniformity from the finite source-to-sample distance is compensated by pre-adjusting junction dimensions. Electrode thicknesses are also engineered for quasiparticle protection: a gap difference exceeding h x 10 GHz, larger than typical qubit frequencies, is obtained, for example, with a 10 nm bottom and 100 nm top electrode. Excess metal is removed by lift-off.

Stage 3: Patch layer. A final patch establishes reliable contact between the base and junction layers. After ion-milling the patch region, Al is evaporated and lifted off, completing the processor.

Scalability is extended through out-of-plane interconnects: flip-chip bump bonding separates quantum and control chips, with an optional TSV chip for isolation, while pogo pins, machined structures, or adhesives provide alternatives.

Intrinsic limitations. Because metal is deposited after resist patterning, the pristine substrate-metal interface is disrupted by air exposure, high-temperature-deposited materials are incompatible with organic resist, and dangling resist polymers can contaminate the barrier and drive junction aging. Angled evaporation also remains sensitive to resist height. These issues motivate etch-based, foundry-compatible flows.

A.2 Toward Foundry-Compatible Wafer-Scale Fabrication

Scaling demands a transition from bespoke academic processes to standardized, high-throughput foundry flows while preserving ultra-low-loss materials and interfaces. The roughly 100 nm critical dimension of a JJ lies within deep-UV (DUV) photolithography limits, so DUV can replace the slower, charging- and scattering-prone electron-beam lithography (EBL) traditionally used. Two DUV-compatible routes have emerged.

Tri-layer process. All superconducting and insulating layers are deposited before any lithography, enabling atomic-level barrier control across the wafer. Because critical current density depends exponentially on barrier thickness and critical current scales with area, this suppression of thickness variation, combined with DUV patterning and anisotropic dry etching, markedly improves wafer-scale uniformity relative to lift-off. The central difficulty is routing current between bottom and top electrodes without shorts. Early flows used permanent dielectric isolation, which raised dielectric loss and lowered coherence. A removable SiO2 spacer overcomes this: it isolates electrodes during wiring, then is selectively removed. Because the spacer sits beneath the wiring, removal requires careful chemistry; aggressive isotropic etching risks junction damage and incomplete removal leaves lossy residue. Nb/Al-AlOx/Nb trilayer junctions with an optimized selective wet etch reached coherence approaching 60 microseconds, with vapor-phase HF (VHF) offering more conformal removal from confined geometries.

Layer-by-layer process. Each junction layer is patterned in an independent lithography step, eliminating sacrificial isolation dielectrics. Depositing the bottom metal before lithography preserves substrate surface treatments and allows ultra-high-vacuum tools; anisotropic etching yields clean sidewalls and reduced line-edge roughness; and the barrier forms without organic resist. The key challenge is the vacuum break between depositions, which forms native oxide that must be removed by ion milling, where overmilling introduces TLS and roughness and undermilling leaves residual oxide. All-Al variants pattern the bottom electrode, ion-mill and oxidize to form AlOx, then deposit and pattern the top electrode; a planarized variant uses a patterned SiO2 spacer with via windows for controlled oxidation, removed by VHF at the end. Foundry-compatible fluxonium qubits made this way reached lifetimes exceeding 1 ms (with evaporation retained for the top electrode), though critical-current-density uniformity may trail the precisely engineered tri-layer barrier, posing a flexibility-versus-control trade-off.

A.3 Integration of Novel Junction Materials

Emerging materials follow a staged pathway from proof-of-concept to scalable integration. Mechanical exfoliation and transfer is a validation platform rather than a manufacturing route, isolating high-quality flakes while minimizing grain boundaries; interface-preserving strategies include in-vacuum exfoliation, h-BN encapsulation, membrane-assisted exfoliation, and trap-free transfer, realized through viscoelastic stamping, pick-up, tear-and-stack (for twist control), and patterned transfer. Throughput and wafer-scale uniformity remain fundamental limits. Direct growth must eventually replace exfoliation: MBE is the benchmark for crystalline, low-defect films but is throughput-limited; ALD provides conformal atomic-scale barriers; sputter and PVD integrate well with existing flows; and CVD enables large-area 2D vdW growth, though grain boundaries and nonuniform stoichiometry persist. For conventional superconductors, CMOS-compatible 300 mm routes (for example ALD TaN, sputtered Al with controlled oxidation on high-resistivity Si) trade some crystallinity and interface abruptness for process compatibility. Finally, MEMS integration offers post-fabrication tunability and correction, adjusting twist angle, interlayer spacing, and strain, and suppressing wrinkles and trapped bubbles that generate charge traps and dielectric loss, an attractive route for twist-angle-sensitive devices.

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