Concepts

• Opcode: the code that indicates the instruction, each architecture has a different way to encode its instruction set
• Programming model: the microprocessor interface to programmers, exposing available resources, e.g. instructions, registers, etc.
• Instruction set architecture (ISA) is combination of programming model (what registers/processing units/etc. are available, etc.) and instruction set (what users can do with the registers, etc.) of a microprocessor.
• The processor’s microarchitecture is its hardware implementation of its ISA: how the circuitry, etc. in that microprocessor handles the features…
• Fetch-execute cycle: 4 steps: fetch, decode, execute, write
• Clock is a quartz crystal circuit that generates a constant electric pulse, that is a wave alternating between low and high voltages (indicating 0 and 1)
  • dictates how long the processor takes to execute 1 step in the fetch-execute cycle
    • modern CPUs are triggered to execute 1 step when voltage jumps from 0 to 1 (rising edge)
    • more detailed: data are stored in registers, which consist of flip flops. Flip flops are essentially turnstiles that only allow signals flow through when the rising edge generated by the clock
    • Why need preventing signals flowing continuously? (i.e. synchronous vs async clock CPU design)
      • one advantage: less complexity: suppose we need 2 signals A and B for the result, A travels through 1 gate but B travels through 10 gates ⇒ when mismatch when combining data at the end! (10th A signal matched with 1st B signal!!!) ⇒ better synchronized!

Register file

array of register…

need read and write ports for communication…

Pipelining

Pipelining is to break down the CPU execution into discrete steps that can be completed in sequence by specialized hardware and to overlap the execution of different steps simultaneously.

Pipelining doesn’t reduce the time to execute each instruction, but it does reduce the total time to execute the whole program. However, pipelining might increase instruction exec time…comes with

…

Pipeline stall is when the execution of 1 stage takes longer than other stages, hence later jobs are stalled until the current is done and passed to the next stage. ⇒ may use out of order execution to increase efficiency!

Superscalar execution

Scalar execution is to have 1 ALU unit and do 1 instruction at the same

Superscalar execution is the practice to put multiple ALUs and execute multiple instructions at once.