Group: Timing Systems Group (TSG)
Summary
Location: Bangalore
Job type: Full time
Work Policy: 100% in-office
Joining Date: Immediately
Minimum Experience: 4+ yrs
CTC: Don’t worry we value your talent
About the Role
We are building the next-generation Global LEO-PNT (Positioning, Navigation, and Timing) satellite constellation from India. We are looking for a highly motivated FPGA Engineer to design, implement, and verify FPGA and firmware architectures that power VyomIC’s onboard GNSS receiver, timing, and payload systems. The role involves RTL development, hardware integration, embedded firmware, high-speed digital design, and implementation of advanced signal processing algorithms for real-time satellite applications. You will collaborate closely with hardware, signal processing, GNSS, and mission teams to bring receiver and timing architectures from concept to silicon.
Key Responsibilities
- Design, develop and maintain FPGA firmware using VHDL, Verilog and Embedded C for onboard receiver and timing subsystems.
- Implement complete FPGA development flow including RTL design, synthesis, implementation, place-and-route, timing closure and bitstream generation.
- Develop simulation environments, testbenches and verification methodologies to validate RTL functionality.
- Perform waveform analysis, debugging and design modifications based on verification results.
- Integrate FPGA firmware with onboard hardware, embedded software and high-speed digital interfaces.
- Develop and debug communication interfaces including I2C, SPI, UART, Ethernet, RS422, RS485 and CAN protocols.
- Implement advanced FPGA algorithms including Kalman Filtering, Digital Signal Processing (DSP), FFT, NCOs, correlators, synchronization and fixed-point designs.
- Implement PRN encoding for navigation message generation supporting onboard GNSS payload operation.
- Work with Microchip/Microsemi Libero SoC, SoftConsole and MATLAB for firmware development, synthesis and embedded software integration.