PCIe (Peripheral Component Interconnect Express)

https://www.youtube.com/watch?v=PrXwe21biJo

https://topofmind.dev/blog/2026/02/15/gpu-virtualization-part-1-an-introduction-to-pcie-and-mmio/#topology-considerations

PCIe is a high speed bidirectional serial link (meaning bits travel sequentially, one bit at a time and can travel in both directions at a given time)

History

• Early IBM PCs came with Industry Standard Architecture (ISA) slots and everything connected to these early on - the problem was that ISA slots were not fast enough
  • EISA and VLB were introduced later to address this
  • 1992 introduced the Peripheral Component Interconnect expansion slot
  • GPUs were connected to Accelerated Graphics Port (AGPs) but they were incompatible across versions and GPUs
  • PCIe launched in 2004 as a higher speed version of PCI
• PCIe slots can come in multiple sizes (lanes)

Lanes

• A PCIe lane is a serial connection for data transfer
• PCIe x4 has 4 lanes and increases the throughput by 4x in comparison to one lane, without having to increase the speed of the underlying technology
• PCIe versions - each version roughly doubles the speed (amount of data transfer per lane)
• PCIe 5.0 has about 4 Gbps of throughput in a single lane
• In most cases, the physical size represents the number of lanes
• You can put a lower lane component into a higher lane slot if needed
• If you connect a PCIe 3.0 card into a PCIe 2.0 slot, the speed & throughput will be bounded by the PCIe 2.0 slot

Topology

• PCI uses a parallel bus architecture, where all devices share a common set of address, data, and control lines